A multiple-times programming (MTP) memory cell retains information stored in the memory cell even when the power is turned off. To create a MTP memory cell, typically, a standard CMOS-based logic process is used as a starting foundation. Next, additional process steps are incorporated into the logic process flow to create the MTP memory cell. Examples of such additional process steps include second polysilicon deposition, junction dopant optimization, etc. Integrating MTP-specific process steps into the standard CMOS-based logic process creates complications. Consequently, embedded MTP memory technologies generally lag behind advanced logic fabrication processes by several generations. For a system-on-chip (SOC) approach, which requires embedding a MTP memory, a design team typically has no choice but to accept a logic flow process usually two to three generations behind the current advanced standard logic process as well as an additional seven to eight lithographic masks in addition to that process. This prior approach not only increases the wafer cost, but it also falls short of the peak performance that the most advanced standard logic process can deliver.
Structures and fabrication methods have therefore been explored to solve the above-discussed problems. FIG. 1 illustrates a perspective view of a conventional MTP memory cell 100, which includes transistor 102, first capacitor 104, second capacitor 106, and third capacitor 108. First capacitor 104, second capacitor 106 and third capacitor 108 share a common floating gate 110. Transistor 102 is controlled by word-line 120, which determines whether a voltage applied on bit-line 122 can be applied into memory cell 100 or not. Source line 124 is connected to transistor 104.
In one embodiment, the program and erase operations of MTP memory cell 100 are achieved by tunneling electrons into and out of floating gate 110. For example, to program MTP memory cell 100, a high voltage is applied to program gate 112, while erase gate 114 is grounded. Due to the capacitive coupling of the coupling capacitors 106 and 108, a large voltage drop is produced across the two plates of tunneling capacitor 108, resulting in a high electrical field between the two plates. When the electrical field is sufficiently high for Fowler Nordheim tunneling to occur, electrons in floating gate 110 tunnel through the insulating material between floating gate 110 and the connecting well region 116.
Conversely, by applying a high voltage to erase gate 114 and program gate 112, electrons can tunnel out of floating gate 110 to source line 124, and thus the negative charge in the floating gate is reduced.
The MTP memory cell 100 shown in FIG. 1 suffers drawbacks, however. Since erase gates of all memory cells in a column are interconnected, and program gates of all memory cells in a row are interconnected, in order to erase a selected memory, high voltages need to be applied to the respective column and row of the selected memory cell. Accordingly, all the array, in which the selected memory array is located, needs to be erased. In addition, high voltages adversely causes program disturbance to other rows and columns. Furthermore, erase gates are formed of big well regions. Erase gate well regions 118 of memory cells in a same row have to be electrically disconnected from each other since they need to be connected to different voltages. The neighboring well regions 118 in a row also need to have adequate well spacing. This results in an increase in the size of the memory cells.
What is needed, therefore, is an improved MTP memory cell and array structure having reduced program disturbance and requiring less chip area.